Università degli Studi di Siena
Department of Information Engineering and Mathematics (DIISM)
Course of
High-Performance Computer Architecture 2024-2025
 
 
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 OBJECTIVES
Knowledge of the techniques for supporting the parallelism in computer systems. Ability to implement parallel applications.
 PREREQUISITES
Computer Architecture 1
 SYLLABUS
* Introduction, Pipeline review. * Dynamic Instruction Scheduling * Tomasulo: An Efficient Algorithm for Exploiting Multiple Arithmetic Units * Branch Prediction: speculation of branch condition and branch target. * Predictor types, Bimodal, BHSR, BHT, PHT, 2-level adaptive. Other predictors (gshare, gselect). * Introduction to Superscalar Processor: general scheme and Renaming. * Full-System Simulator for single-core and multi-core systems. * Superscalar execution example: Re-Order Buffer and Instruction Window. Case studies: MIPS, Alpha, AMD, Pentium. * Software methods to extract Instruction Level Parallelism. * Introduction to multiprocessor systems, Flynn's taxonomy, UMA, NUMA, COMA systems, programming models * Coherence Protocols: Write Update, Write Invalidate, Hybrid. Snoopy based protocols: the MESI and DRAGON protocols * Memory Consistency Models: Sequential Consistency and Relaxed Consistency * Introduction to parallel programming. * Parallelsim and Performance * CUDA Architecture and Programming Elements * Introduction to OpenMP, Cilk, OpenMPI, Dataflow programming models. * Advanced topics: reconfigurable computing; datacenters.
 TEXTBOOKS
REFERENCE (ADOPTED) TEXTBOOKS

SUGGESTED (OPTIONAL) TEXTBOOKS
  • J.L. Hennessy, D.A. Patterson, "Computer Architecture: A Quantitative Approach" 6th Edition, Morgan Kaufman/Elsevier, 2019, ISBN: 978-0-12-811905-1
  • D. Culler, J.P. Singh, A. Gupta, "Parallel Computer Architecture: A Hardware/Software Approach", Morgan Kaufman/Elsevier, 1998, ISBN-10 1558603433.
  • M.J. Flynn, "Computer Architecture: Pipelined and Parallel Processor Design", Jones and Bartlett Publishers, Inc., 1995, ISBN 0867202041
  • David B. Kirk and Wen-mei W. Hwu, "Programming Massively Parallel Processors: A Hands-on Approach", 3rd ed., Morgan Kaufmann (2019) ISBN 978-0-12-811986-0.

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